1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly to low power consumption type semiconductor static RAMs having bit line potential compensation circuits.
2. Description of the Related Art
A conventional low power consumption type semiconductor static RAM of the kind to which the present invention relates is first explained with reference to FIG. 1 showing the circuit structure, FIG. 2 showing the circuit structure of a memory cell shown in FIG. 1, FIG. 3A showing a timing chart in a write operation of the static RAM, and FIG. 3B showing a timing chart in a read operation of the static RAM. The static RAM comprises an address buffer circuit 51, an address transition detection circuit 52, an internal clock generation circuit 53, a row decoder circuit 54, a column decoder circuit 55, a sense amplifier circuit 56, an input/output buffer and output latch circuit 57, a write/read control circuit 58, a write driver circuit 59, bit line load circuits 60.sub.1 to 60.sub.n, bit line potential compensation circuits 61.sub.1 to 61.sub.n, and a memory cell array 62.
To the address buffer circuit 51, external address input signals A.sub.0 to A.sub.n are supplied. Of the outputs of the address buffer circuit 51, upper bits A.sub.0 ', . . . are supplied to the row decoder circuit 54, and lower bits A.sub.n ', . . . are supplied to the column decoder circuit 55. The upper and lower bits are also supplied to the address transition detection circuit 52.
An output OS of the address transition detection circuit 52 is supplied to the internal clock generation circuit 53. This internal clock generating circuit 53 provides an output XE supplied to the row decoder circuit 54, an output SE supplied to the sense amplifier circuit 56, and an inversion output P (hereinafter referred to as "P*", the asterisk notation (*) being used throughout the disclosure to indicate the inversion or binary complement) supplied to the bit line load circuits 60.sub.1 to 60.sub.n.
The write/read control circuit 58 receives a read/write output signal WE*, and provides an output which is supplied to the internal clock generation circuit 53 and also to the write driver circuit 59. The write driver circuit 59 provides an output WCL which is supplied through the input/output buffer and output latch circuit 57 to output I/O terminals, an output WBT supplied through transfer gates Q.sub.05, Q.sub.07 to Q.sub.n5, Q.sub.n7 to bit lines B.sub.0 to B.sub.n, and an output WBB supplied through transfer gates Q.sub.08, Q.sub.06 to Q.sub.n8, Q.sub.n6 to bit lines B.sub.0 * to B.sub.n *,
The row decoder circuit 54 provides outputs W.sub.0 to W.sub.n supplied respectively to word lines of the memory cell array 62. The column decoder circuit 55 provides an output which controls the gate electrode of each of the transfer gates Q.sub.05, Q.sub.07 to Q.sub.n5, Q.sub.n7, and Q.sub.08, Q.sub.n6 to Q.sub.n8, Q.sub.n6.
The bit line potential compensation circuits 61.sub.1 to 61.sub.n are inserted between the bit line load circuits 60.sub.1 to 60.sub.n and the memory cell array 62. In the memory cell array 62 to which the bit line potential compensation circuits 61.sub.1 to 61.sub.n are connected, input/output data of memory cells MC.sub.00 to MC.sub.n0 are supplied to the bit line B.sub.0 and the bit line B.sub.0 *, and input/output data of memory cells MC.sub.0n to MC.sub.nn are supplied to the bit line B.sub.n and the bit line B.sub.n *,
In the semiconductor static RAM as described above, it is attempted to reduce the current to flow from the bit line load circuits 60.sub.1 to 60.sub.n to selected memory cells and also the current to be consumed in the sense amplifier circuit 56.
First, when reading data, the address transition detection circuit 52 detects a change in the external address input signal A.sub.n and outputs a pulse signal OS. The internal clock generation circuit 53 that receives the signal OS outputs a bit line load control signal P*, a word line control signal XE and a sense amplifier control signal SE, these signals being pulse signals having pulse width necessary for the read operation. The signals XE and P* restrict the active period of the word line W and the active period of the sense amplifier circuit 56 to their pulse durations. In this way, the active period of the word line W is made short and constant irrespective of the read cycle time.
Now, the bit line load circuit 60.sub.1 and the memory cell MC.sub.00 are considered as an example. The current which flows from the bit line load circuit 60.sub.1 to the selected memory cell MC.sub.00 is restricted. A pair of P-channel MOS transistors Q.sub.01 and Q.sub.02 of the bit line load circuit 60.sub.1 are controlled by the pulse signal P* which is synchronized to the word line control signal XE, whereby the bit line load circuit 60.sub.1 is held "off" while the word line W.sub.0 is active. Thus, while the word line W.sub.0 is active, current to flow from the bit line B.sub.0 and bit line B.sub.0 * into low level nodes of the memory cell MC.sub.00 corresponds only to the charge that is stored in the line capacitance of the bit line B.sub.0 or bit line B.sub.0 *,
When writing data, in order to guarantee write data change in the write cycle period and prohibit the operation of the sense amplifier which consumes a large amount of current, the word line W.sub.0 is not controlled pulse-wise and, after it is turned active, the bit line load circuit 60.sub.1 is not turned off until the end of writing of data with an external input signal.
However, as in the read operation, the bit line load circuit 60.sub.1 is controlled in synchronism to the word line W.sub.0, and it is held "off" while the word line W.sub.0 is active.
As an example, when writing data of a high level "1" in the memory cell MC.sub.00, the column decoder circuit 55 selects the bit line B.sub.0 and bit line B.sub.0 *, and the write driver circuit 59 provides a high level voltage in logic level to the bit line B.sub.0 and a low level voltage in logic level to the bit line B.sub.0 *. In the active state of the word line W.sub.0, the high and low level voltages are written in the nodes N1 and N2 of the memory cell MC.sub.00 shown in FIG. 2.
However, for example, the memory cell MC.sub.0n which is one of the non-selected memory cells other than the memory cell MC.sub.00 connected to the selected word line W.sub.0 outputs data that are held therein to the bit line B.sub.n and bit line B.sub.n *. Assuming that high level data "1" is held at the node N1, the charge stored on the bit line B.sub.n * connected to the node N2 which is held at low level, flows through a drive transistor Q.sub.8 of the memory cell MC.sub.0n into the ground potential GND, so that the potential at the bit line B.sub.n * is eventually reduced from a supply voltage V.sub.cc to about the ground potential GND.
Before the word line W.sub.0 is turned active, the bit line B.sub.n is held at the supply potential V.sub.cc. Thus, when the word line W.sub.0 is turned active, the node N1 of the non-selected memory cell MC.sub.0n, holding level data "1", is held at the same potential as before, so that the potential on the bit line B.sub.0 is not changed.
In 4 Mbit static RAM class, however, actually 1,024 memory cells are connected to a single bit line, for instance B.sub.0. This means that an N.sup.+ -type diffusion layer (or N-type diffusion layer) forming the source electrodes of transfer transistors Q.sub.3 and Q.sub.4 having the gate electrodes connected to the word line W.sub.0 and the drain electrodes connected to the data storing nodes N1 and N2 in the memory cell MC.sub.00 for storing data, is connected to the bit line B.sub.0 and bit line B.sub.0 * through contact holes for each of 1,024 memory cells.
There is a sub-threshold leakage in the transfer transistor Q.sub.3 or Q.sub.4 connected to the node N1 or N2 in which the low level data is stored. There is also a junction leakage in the N-type diffusion layer forming the source electrodes. If these leakage currents are greater than the current that is supplied from load transistors M.sub.5 and M.sub.6 of the memory cell MC.sub.00, the charge stored at the bit line B.sub.0 or bit line B.sub.n * for which the bit line load circuit 60.sub.1 is "off" is reduced.
That is, at the non-selected memory cells MC.sub.01 to MC.sub.0n which are connected to the selected word line W.sub.0, the potential on the bit line connected to the node N1 or N2 holding high level data is reduced with the lapse of time. Where the write period is as long as 1 msec., for instance, the active period is also about 1 msec., as described before. During this time, the high level potential at the bit line B.sub.0 or bit line B.sub.n * is reduced, and if it becomes lower than the threshold voltage of the drive transistors Q.sub.5 and Q.sub.6, the data that has been held in that memory cell is destroyed.
The operation of the bit line potential compensation circuit 61.sub.1, as an example, will now be described. This circuit comprises two P-channel MOS transistors Q.sub.03 and Q.sub.04 each having the gate electrode connected to the drain electrode of the other. The P-channel MOS transistors Q.sub.03 and Q.sub.04 have their drain electrodes connected to the bit line B.sub.0 and bit line B.sub.0 *, respectively.
When the P-channel MOS transistor Q.sub.03 is turned on with reduction of the potential at the bit line B.sub.0 * connected to the node N2 of the memory cell MC.sub.00 holding low level data from the supply potential V.sub.cc, a further charge is supplied therefrom to the bit line B.sub.0, to which the high level data is supplied from the node N1. This has an effect of preventing the potential level reduction of the bit line B.sub.0 due to the leakage.
Further, the potential at the bit line B.sub.0 providing high level data is not reduced earlier than the bit line B.sub.0 * providing low level data, so that the P-channel MOS transistor Q.sub.04 with the drain electrode thereof connected to the bit line B.sub.0 is not turned on.
Referring now to FIG. 4, which is a plan view showing the element arrangement of the P-channel MOS transistors Q.sub.03 and Q.sub.04 of the bit line potential compensation circuit 61.sub.1, this circuit 61.sub.1 has P-type diffusion layers 18 and 19, polycrystalline silicon layers 20 and 21, aluminum interconnects 22 to 26, and contact holes 27 to 34. The aluminum interconnects 23 and 25 constitute the bit line B.sub.0, and the aluminum interconnects 22 and 26 constitute the bit line B.sub.0 *. The aluminum interconnect 24 is led to the power supply line V.sub.cc. The P-channel MOS transistor Q.sub.03 for bit line potential compensation is obtained with the aluminum interconnect 24 of the power supply line V.sub.cc connected through the contact hole 32 to the P-type diffusion layer 19 so as to form the source electrode, the aluminum interconnect 25 of the bit line B.sub.0 connected through the contact hole 33 to the P-type diffusion layer 19 to constitute the drain electrode, the aluminum line 26 of the bit line B.sub.0 * connected through the contact hole 34 to the polycrystalline silicon layer 21, and the polycrystalline silicon layer 21 thus constituting the gate electrode.
Likewise, the P-channel MOS transistor Q.sub.04 for bit line potential compensation is obtained with the aluminum interconnect 24 of the power supply line V.sub.cc connected through the contact hole 29 to the P-type diffusion layer 18 to constitute the source electrode, the aluminum interconnect 22 of the bit line B.sub.0 * connected through the contact hole 28 to the P-type diffusion layer 18 to constitute the drain electrode, and the aluminum interconnect 23 of the bit line B.sub.0 connected through the contact hole 27 to the polycrystalline silicon layer 20 so that this layer constitutes the gate electrode. The shaded regions show channel regions of the P-channel MOS transistors Q.sub.03 and Q.sub.04 for bit line potential compensation.
The P-channel MOS transistors Q.sub.03 and Q.sub.04 for bit line potential compensation are necessary for all bit line pairs. Therefore, they have to be laid out such that they are accommodated in substantially the same width as the width of the arrangement of the bit line B.sub.0 and bit line B.sub.0 * extending in parallel in the memory cell. They also have to be laid out in a rectangular shape with the longer sides thereof parallel to the bit line.
In the recent semiconductor static RAM, because the memory cell array is finely formed, one effect of this is that, at the end portion thereof where such memory cell array is arranged, the exposure of the photoresist is subjected to the light interference during the semiconductor fabrication process due to the presence of density differences of the patterns. This results in size differences between the inner portion and the end portion of the layout. Thus, in order to equalize the pattern sizes of the regular memory cells, the pseudo memory cells are arranged in a line for each pair of bit lines at the outermost periphery of the memory cell array on the side at which the bit line load circuit is connected.
In semiconductor static RAMs of 1 Mbit class, high resistivity polysilicon is used for the load elements of memory cells. In 4 Mbit classes and above, thin film transistors of polysilicon, which are load elements, are used for reducing the power consumption without spoiling the data holding property.
Referring now to FIG. 5, which is a plan view showing the structure of a memory cell, for instance, memory cell MC.sub.00, using the thin film transistors noted above as load elements. As shown, the memory cell comprises N-type diffusion layers 37 and 38 constituting the source electrode and drain electrode regions of N-channel MOS transistors Q.sub.5 and Q.sub.6, a first polycrystalline silicon layer 39 constituting the gate electrodes of transfer transistors Q.sub.3 and Q.sub.4 and also a word line, second polycrystalline silicon layers 40 and 41 constituting the gate electrodes of thin film transistors M.sub.5 and M.sub.6, third polycrystalline silicon layers 42 and 43 constituting the source electrodes, channels and drain electrode regions of the thin film transistors M.sub.5 and M.sub.6, aluminum interconnects 44 and 45 of bit line B.sub.0 and bit line B.sub.0 *, first polycrystalline silicon layers 46 and 47 constituting the gate electrodes of drive transistors Q.sub.5 and Q.sub.6, contact holes 48, 49 and 50 for connecting the N-type diffusion layers 37 and 38 and first polycrystalline silicon layers 46 and 47 to one another, and contact holes 53 and 54 for connecting the third polycrystalline silicon layers 42 and 43 constituting the drain electrodes of the thin film transistors M.sub.5 and M.sub.6, second polycrystalline silicon layers 40 and 41 constituting the gate electrodes of the thin film transistors M.sub.5 and M.sub.6, first polycrystalline silicon layers 46 and 47 as lower layers and N-type diffusion layers 37 and 38 to one another, and contact holes 53 and 54 for connecting the bit line aluminum interconnects and N-type diffusion layers to one another.
FIG. 6 also shows the structure of the memory cell shown in FIG. 5, in a sectional view taken along line 6--6 in FIG. 5. In FIG. 6, the numeral 70 represents a silicon substrate, and the numeral 71 represents an element isolation silicon oxide film.
With a recent trend for increasing memory capacity, the semiconductor chip area is increasing to reduce the number of chips that can be obtained by exposure with a single silicon wafer. Naturally, the number of good chips obtainable from a single silicon wafer is reducing.
In the bit line potential compensation transistors noted above, the bit line leakage current is about several pA, and about several nA at the most, whereas sufficient current that is needed is about 100 nA, i.e., about 100 times the leakage current. In addition, recently there is a method of substituting redundant bit lines for defective bit lines that is adopted in redundancy circuit techniques. However, since short-circuiting of a defective bit line to the ground potential GND results in a current passed through the bit line potential compensation transistor, there is no need of designing the current supplied to the compensation transistor to be greater than is necessary.
However, the recent bit line potential compensation transistor is a bulk transistor. In a P-type bulk transistor with a channel length of 1 .mu.m, a channel width of 1 .mu.m and an oxide film thickness of 15 nm, a current of about 100 .mu.A (V.sub.gs =Vds=5 V) is caused to flow. To reduce this current to about 100 nA, it is necessary to reduce the channel length to 100 .mu.m.
As shown in FIG. 5, however, the bit line potential compensation transistor has to be realized with the same element arrangement length as the distance between the bit line B and bit line B* (inclusive of the bit line width) of memory cell. This means that the channel length direction is parallel to the bit line.
To reduce the compensation current supply capability, therefore, the channel length should be extended by 1,000 .mu.m in the direction parallel to the bit line, which leads to a corresponding chip area increase.